This invention relates to clock signal circuits, and more particularly to a method and system for controlling the duty cycle of an output clock signal independently of the duty cycle of an input clock signal.
Clock signals are commonly used for a variety of purposes in digital systems, such as memory devices. For example, in a synchronous dynamic random access memory (xe2x80x9cSDRAMxe2x80x9d), a clock signal is used to determine the time at which control, data and address signals applied to the SDRAM are considered valid. The control, data and address signals are then latched into the SDRAM responsive to a transition of the clock signal.
In some cases, the duty cycle of the clock signal is not critical. For example, if the clock signal is used to latch a memory control signal once for each period of the clock signal, the control signal will be latched at the proper time regardless of whether the clock signal has a 50% duty cycle. However, controlling the duty cycle is critical in other applications. For example, in xe2x80x9cdouble data ratexe2x80x9d DRAMs, control, data and/or address signals are latched on each transition of the clock signal, i.e., on both the rising and falling edges of the clock signals. If the clock signal does not have a 50% duty cycle, the latching of the signals will not be symmetrical, and the clock signal may therefore fail to properly latch the signals.
The duty cycle of a clock signal can become skewed, i.e., vary from a 50% duty cycle, for a variety of reasons. For example, the clock signal may be coupled through a switching circuit that changes state when the clock signal has a predetermined voltage relative to the power supply voltage. In such case, power supply noise can momentarily increase or decrease the supply voltage, thereby altering the time at which the clock signal transitions. The duty of the clock signal can then vary from cycle-to-cycle. In other cases, the components used in a circuit having a symmetrical topography do not have the same electrical characteristics, thus causing them to operate differently. For example, a first transistor used in the circuit may have a resistance or threshold voltage that is different from the resistance or threshold voltage of a second transistor used in the circuit. In such cases, the duty cycle will be constant from cycle-to-cycle, but the duty cycle will vary from 50%.
There is therefore a need for a system and method for controlling the duty cycle of a clock signal in a manner that is not affected by variations in power supply voltage or electrical characteristics of circuit components, so that a clock signal having a duty cycle of 50% or some other value can be generated.
A method and system for generating an output clock signal having a controllable duty cycle from an input clock signal in accordance with the invention includes a duty cycle corrector circuit coupled to a duty cycle indicating circuit through a control circuit. The duty cycle corrector circuit is structured to transition the output clock signal to a first logic level responsive to a first transition of the input clock signal after a first delay that corresponds to a first control signal. The duty cycle corrector circuit is also structured to further transition the output clock signal to a second logic level that is different from the first logic level responsive to a second transition of the input clock signal that is different from the first transition of the input clock signal after a second delay that corresponds to a second control signal. The duty cycle indicating circuit is coupled to receive the output clock signal, and it generates a duty cycle feedback signal corresponding to the duty cycle of the output clock signal. The control circuit is structured to generate the first and second control signals as a function of the duty cycle feedback signal so that the first and second delays are selected to cause the output clock signal to have a predetermined duty cycle.